The present invention relates generally to the field of processors and in particular to a method of conditional instruction execution via an emissary instruction for condition evaluation.
Microprocessors perform computational tasks in a wide variety of applications. High execution speed, low power consumption and small size are commonly important goals for processor designers, particularly in embedded applications such as portable electronic devices. An important consideration, however, is accuracy. Whatever architectural features are included in the processor design to improve execution speed or other metric needs also to assure the correct execution of software code.
Many modern processors employ a pipelined architecture, where sequential instructions, each having multiple execution steps, are overlapped in execution. For improved performance, the instructions should flow continuously through the pipeline. However, instructions may become stalled in the pipeline for a variety of reasons, such as data dependencies between instructions, also known as data hazards. High performance processors may employ a superscalar design, where part of the pipeline is replicated. Multiple pipelines can minimize the effect of pipeline stalls on overall system performance, as instructions awaiting a stalled pipeline may be dispatched to another pipeline for immediate execution.
To take maximum advantage of the potential performance gain offered by superscalar pipelines, high performance processors commonly support out-of-order execution. That is, instructions may be executed in other than their program order, if doing so is not precluded by inter-dependencies among the instructions. As one example of such dependencies, an instruction performing a logical or arithmetic operation that reads an operand from a register cannot execute until a prior instruction, that writes a result to that register, has calculated its result (data can be forwarded, where completed may imply the instruction has left the pipeline). These two instructions cannot be executed out of order, or an incorrect result will occur. The process of detecting dependencies among instructions is known as hazard detection. Hazard detection is commonly performed very early in the pipeline, prior to dispatching instructions into an execution pipeline.
Most instruction set architectures include conditional instructions, which are instructions that perform some operation—or not—depending on the evaluation of a condition. Condition evaluation is typically performed in an execute pipe stage, deep in the pipeline. Conditional instructions can greatly complicate hazard detection by delaying knowledge of whether the operation will be executed until deep in the pipeline. However, knowledge of whether or not the operation will affect, e.g., the contents of a register, is required early in the pipeline for hazard detection. The following example code segment illustrates this problem:
ADDr1, r7, r8add contents of r7 and r8, place sum in r1CMPr1, r12compare contents of r1 and r12 (set code or flagto reflect the result of the comparison)ADDEQr1, r8, r9if the previous compare was equal, add contentsof r8 and r9 and place sum in r1. Otherwise,r1 is not changedADDNEr1, r3, r4if the previous compare was not equal, addcontents of r3 and r4 and place sum in r1.Otherwise, r1 is not changedANDr10, r6, r1logical AND the contents of r6 to the contentsof r1, place the result in r10
The final AND instruction has an r1 dependency on the ADDNE instruction. That is, the ADDNE must calculate its result prior to the AND executing, so that the data written into r1 by the ADDNE will be available to the AND. However, the ADDNE is a conditional instruction, and may not execute the ADD operation. In this case, the true dependency of the AND instruction is on the ADDEQ instruction. In the foregoing example (depicting a common software construct), exactly one of the ADDEQ and ADDNE instructions will execute, since the conditions EQ (equal) and NE (not equal) are mutually exclusive and exhaustive. However, in general, since the ADDEQ instruction is conditional, the AND may actually have a dependency on an earlier instruction, in this case the initial ADD. Additionally, if a prior conditional instruction does not execute, a following instruction may have no dependency at all.
The contingent dependencies presented by conditional instructions, and in particular the possible multi-level contingent dependencies, greatly complicate the task of accurate hazard detection, which is necessary for accurately conducting out-of-order program execution.